The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to selective deposition of dielectrics on ultra-low k dielectrics.
Advancements in semiconductor fabrication have enabled the manufacture of integrated circuits with high densities of electronic components. However, the increasing numbers and lengths of interconnect wirings can increase circuit resistance-capacitance delay and power consumption, which could impact circuit performance.
Three-dimensional (3D) stacking of integrated circuits addresses the afore-mentioned challenges. Fabricating 3D integrated circuits includes vertically stacking wafers to form a multilevel structure. Vertically stacking the wafers can reduce interconnect wiring length and increase semiconductor device density.
A typical process for fabricating a single wafer level in a multilevel structure includes depositing a dielectric material, patterning the dielectric material to form openings (including trenches and vias), depositing a conductive material onto the wafer in sufficient thickness to fill the openings, and removing excessive conductive material from the surface using a chemical, mechanical, or combined chemical-mechanical polishing techniques.